1. Field of the Invention
The present invention relates to a circuit board for mounting a semiconductor chip used in a semiconductor device in which a semiconductor chip is packaged, such as a Ball Grid Array (BGA), a Land Grid Array (LGA) or a Chip Size Package (CSP), and also relates to a manufacturing method thereof.
2. Description of the Related Art
In recent years, many external terminal connection terminals have become necessary due to increases in the speed and sophistication of signal processing of semiconductor chips. Thus, as one semiconductor chip package, there is a BGA-type semiconductor device where external terminals are arranged two-dimensionally on a bottom surface thereof. For example, there is a BGA-type semiconductor device where a semiconductor chip is mounted on a circuit board, on which are disposed solder balls arranged two-dimensionally as external electrodes, and the vicinity of the semiconductor chip is sealed with a resin. On this circuit board, wirings electrically connected to external terminals of the semiconductor chip are formed on an insulating substrate, a solder resist (protective film) that protects these wirings is formed, and the semiconductor chip is laminated on a surface of the solder resist.
In this BGA-type semiconductor device, when the semiconductor chip is mounted on a printed board such as a mother board, the two-dimensionally arranged solder balls are soldered at once by reflow on plural pads on the printed board.
However, there is the problem that the circuit board becomes warped due to thermal stress resulting from the reflow. In order to prevent such warping, a reinforcement layer comprising copper or the like has conventionally been formed on the circuit board.
In this circuit board, as shown in FIGS. 6 and 7, the reinforcement layer is formed in a region (reinforcement layer region 132) positioned in a substantially central portion of a circuit board 110 at an inner side of a wiring region 128 (or at inner sides of wiring regions 128) where wirings connected to the external terminals of the semiconductor chip are formed on an insulating substrate 116, whereby the semiconductor chip is mounted above the reinforcement layer region 132.
However, as shown in FIG. 8, when a solder resist 122 is formed so as to cover wirings 118 and a reinforcement layer 120, the surface of the solder resist 122 is uneven along the pattern of the wirings 118 and the reinforcement layer 120, and the semiconductor chip adhering surface is not planar. Thus, for example, problems arise in that pressure from the chip at the time of mounting the semiconductor chip becomes unevenly applied to the chip adhering surface, a liquid adhesive (die-bonding agent) is not evenly coated, an insufficiently filled portion (void) is generated in a semiconductor chip vicinity portion, and peeling of the semiconductor chip and breakage arise due to thermal stress at the time of reflow.
In order to planarize the semiconductor chip adhering surface, a proposal has been made in Japanese Patent Application Laid-Open Publication (JP-A) No. 11-340249 to form wirings on the insulating substrate and form dummy wirings in regions where these wirings are not formed.
However, in JP-A No. 11-340249, although the semiconductor chip adhering surface is planarized in comparison to what has conventionally been the case, unevenness along the pattern of the wirings and the dummy wirings arises in the chip adhering surface, and there is a demand for further improvement.
The present invention solves the above-described conventional problems and seeks to achieve the following object. Namely, it is an object of the invention to provide a circuit board for mounting a semiconductor chip and a manufacturing method thereof where the circuit board is reinforced in order to prevent post-reflow warping and the chip adhering surface is planarized.